CHIPSTARS Semiconductor | Distributed Edge AI Compute · Chip Design

About CHIPSTARS

About

CHIPSTARS Semiconductor — Chip Design & IP Licensing for Distributed Edge AI Compute

Making Every Edge Device a Distributed Compute Node

CHIPSTARS Semiconductor is aglobal chip design company, headquartered in Shanghai Free Trade Zone, with operations spanning China, Germany, the UK and other major global semiconductor markets. Our core team brings together talent fromTSMC (world's largest foundry), Samsung (world's largest IDM), Qualcomm (world's largest chip design house), and UMC — the world's most elite semiconductor companies.

We believe: NVIDIA dominates centralized cloud compute. CHIPSTARSfocuses on distributed edge compute. Every vehicle, every drone, every industrial terminal — is an independent compute node.

CHIPSTARS is not just a chip design house, but a"Chip + IP + Algorithm + Data"four-in-one edge AI solution provider. We integrate world-class supply chain resources (TSMC, Samsung, Qualcomm), help Chinese clients navigate overseas supply chain challenges, and deliver full-turnkey services from chip design to mass production.

🎯 Strategic Positioning: Localization Backbone + Global Wings

Localization (Backbone)— Building sovereign, secure, and resilient technological foundations. Mastering proprietary IP including PINN Physics-Informed AI and Chiplet architecture, reducing single-source dependency on foreign technology.

Globalization (Wings)— Embracing global standards and competing internationally. Actively collaborating with worldwide research institutions and industry partners to drive international adoption of edge AI chip solutions.

A strong backbone supports powerful wings. They are not in conflict — they are symbiotic.

🎯 Why Edge AI Is a Necessity

Latency Is a Matter of Life and Death — Autonomous driving at 50km/h, 100ms latency = 1.4m braking distance. Edge compute pushes latency to<10ms。

Offline Is the Safety Line — In tunnels, mountains, disaster zones, networks are unreliable. Devices must carry their own "brain".

Data Sovereignty Is a Political Imperative — Industrial, transportation, and energy data cannot go to the cloud. Local AI is a compliance necessity.

Dimension	Centralized Compute (NVIDIA Model)	Distributed Edge Compute (CHIPSTARS Model)
Physical Location	Cloud Data Centers	Vehicle/Aircraft/Drone/IoT Terminals
Latency	ms-sec (network transmission)	Sub-ms (local inference)
Power Consumption	Hundreds of Watts to kW	<15W（edge-optimized）
Network Dependency	Requires real-time connectivity	Runs offline
Data Privacy	Data uploaded to cloud	Local processing, data never leaves device
Business Model	Sell GPU / Compute leasing	Chips + IP licensing + Subscriptions + Data monetization

Product Portfolio

Product & Service Matrix

From Embodied Intelligence to Edge AI, from RF connectivity to LEO satellites — CHIPSTARS covers the full spectrum of distributed compute

🤖 Embodied Intelligence Chip

Building a dedicated "Cerebellum" for embodied intelligence, reconstructing physical-world perception and response with muscle-memory chips. 2026 core investment & fundraising project. In the three-layer embodied intelligence architecture (Brain → Cerebellum → Execution), CHIPSTARS occupies the "Cerebellum" layer — receiving brain commands, focusing on millisecond-level end-point control, distributed computing, and real-time physical environment feedback, becoming the critical neural synapse connecting digital intelligence to physical entities.

Musk open-sourced the dexterous hand algorithm, but hardware integration remains unachieved — CHIPSTARS combinesAlgorithm + Hardware + AIcapabilities to deliver a complete "Hand-Eye-Brain" solution for robots.

Process Node55nm/40nm Mature Process (Phase 1)
Sensor Interface128-256 Channels (full electronic skin coverage)
PWM Drivers23+ Independent Outputs (benchmarking Optimus 22 DOF)
Closed-loop Latency<1ms（touch→action）
Typical Power<500mW
AI EngineIntegrated NPU + DSP cores, edge real-time inference
ArchitectureMulti-core heterogeneous parallel + Event-driven response

📡 RF & Wireless Connectivity IP

The connectivity infrastructure for edge devices. WiFi + Bluetooth dual-mode converged RF IP matrix, covering BLE / dual-mode / RF / Sub-6GHz to mmWave full spectrum. Supports Bluetooth 5.4 (37% lower power) and WiFi 6/7.

BT/WiFi Converged IP:CHIPSTARS BT5.4/WiFi6 dual-mode RF IP matrix, supporting low-power Bluetooth audio, WiFi transparent transmission, coexistence arbitration, and other full functions — MPW verified.

CS1278 Validation Data:June 2026 RF test report shows core RF performance meets specifications — operating frequency 2402-2480MHz, RX sensitivity -95dBm(1M) / -96dBm(BLE), output power -20 to 15dBm, with stable test data.

IP TypeBLE / Dual-Mode / RF / UWB
Frequency CoverageSub-6GHz to mmWave
Process Node22nm / 40nm / 55nm
Coexistence TechnologyPTA Arbitration Mechanism
Coexistence ArbitrationBT/WiFi Dual-Mode Fusion
Licensing ModelIP Licensing + Royalty Sharing + NRE

🛰️ LEO Satellite Communication Chip

Next-generation space communication RF & digital beamforming (DBF) integrated solution. Covering LEO satellite terminals, ground stations, and satellite payloads — providing full-turnkey chip design services from architecture to mass production.

End-to-End Services:RF front-end (LNA/PA/Mixer) + digital beamforming (DBF) baseband co-design, supporting S/C/X/Ku/Ka full bands, extensible to mmWave. Chiplet heterogeneous integration reduces cost by 30-50%.

Application Scenarios:LEO satellite user terminals, ground station RF, satellite IoT, commercial aerospace payloads.

Frequency CoverageS/C/X/Ku/Ka (extensible to mmWave)
RF Front-endLNA + PA + Mixer + Filter
Digital BeamformingDBF Baseband Co-design
Process PlatformCMOS 28nm/22nm, SiGe, SOI
Integration MethodChiplet 2.5D/3D Packaging
Service ModelNRE Custom + IP Licensing + Joint Design

🚗 NEV Chip Design Service Platform

Providing full-turnkey chip design services for new energy vehicles, from spec definition to mass production ramp. Covering SiC power devices, automotive connectivity chips, advanced packaging modules, and other NEV core chip domains. Leveraging the BNA technology platform (DSP/PMIC/AFE), providing full-stack design capability from RTL to GDSII for OEMs and Tier 1s.

Design Capability:1200V trench SiC MOSFET design experience, covering on-resistance optimization, switching loss reduction, and other key performance metrics — delivering SiC power device design services benchmarked against international advanced levels.

SiC Power Devices1200V Trench Design Capability
Automotive ConnectivityBluetooth 5.4 + WiFi 6/7 + UWB
Design ServicesRTL → GDSII Full Flow
Process Node7nm / 12nm / 22nm / 40nm / 55nm
Conversion Efficiency95%+ (Traditional: 85-90%)
ApplicationsTraction Inverter / OBC / DC-DC / Smart Cockpit

🧠 Edge AI Processor + Weather Neural Node

Full Edge AI Inference Chip Matrix + Autonomous Driving "Weather Neural Node". Using Chiplet heterogeneous integration, supporting multi-modal perception and real-time decision-making. From low-power MCU to high-compute weather AI, covering the full spectrum of edge intelligence.

Weather Neural Node:Not replacing the main control chip, but as a core perception enhancement — through localized, physics-consistent meteorological model inference, achieving forward5km road icing, fog patches, crosswind risk prediction, evolving autonomous driving from passive response to active prediction.

Core Moat:Integrated PINN physics-informed AI engine, embedding physical laws into neural networks, eliminating AI hallucinations at the source, achieving automotive-grade absolute reliability.

Edge AI MCU1-4 TOPS, <500mW, PINN Physics-Informed AI
Bluetooth AI ChipBluetooth 5.4 Dual-Mode, 37% Lower Power
WiFi AI ChipWiFi 6/7, Edge AI Processing Unit
Weather AI (MetChip)157 TOPS, <10ms, ASIL-C/D
Functional SafetyASIL-C/D Grade
Automotive GradeAEC-Q100 Grade 2 + IP69K
Beyond-Visual-Line-of-Sight Perception5km Ahead / 90-Second Early Warning

Embodied AI Core

Embodied Intelligence: Millisecond Tactile Closed Loop

Giving robots"a "sense of touch""，not cold code——from perception to action<1msfull-loop closed loop

Distributed Edge Control, Leaving Centralized Compute Bottlenecks Behind

Traditional centralized architectures send thousands of hand sensor data back to CPU/GPU, resulting in excessively long closed-loop latency100ms. CHIPSTARS adoptsDistributed Edge Architecture, pushing decision-making down to local MCUs, with sensor data processed and responded to instantly at the edge.

Core Breakthroughs:<1msLatency · localized closed loop · minimal bus interaction

Millisecond Physical Reflex: Edge-side direct decision-making, 100x+ response speed improvement
Extreme System Power Saving: Central compute load reduced by 70%, significantly extending device battery life
Central Bandwidth Freed: Bus only transmits critical states, letting the "brain" focus on high-level cognition

🔄 Millisecond Tactile Closed Loop Flow

01 Perception Encoding — Real-time encoding of 128-256 sensor channels into high-dimensional "tactile feature vectors"

02 Pattern Matching — 1000+ pre-stored real grasping patterns, rapid retrieval for optimal strategy matching

03 Instant Reflex — sensor trigger to actuator response，full-chain<1ms，rivaling biological neural reflexes

04 Fine-tuning Learning — Central brain pushes optimized muscle-memory models via OTA, "sense of touch" continuously evolving

🎯 Perception Training Ball

Softball-sized soft biomimetic silicone sphere, integrating 128-256 high-precision multi-dimensional sensors, capturing delicate force data from real human hand grasping to build the most realistic tactile database.

🧠 Sim-to-Real

Millions of grasping attempts in virtual simulation, accumulating massive scenario experience at low cost, accelerating model convergence; final policy fine-tuning on physical hardware ensures real-world robustness.

🔄 Reinforcement Learning Closed Loop

Continuously correcting models through feedback mechanisms, final policy fine-tuning on physical hardware to ensure real-world robustness, letting robots continuously evolve in real combat.

Core Technology

Core Technology Moats

Three Technology Pillars Building Unreplicable Competitive Advantage

🔬 Chiplet Heterogeneous Integration

Industrial-grade "LEGO" architecture, splitting a 400mm² chip into four 100mm² chiplets,yield improving from ~50% to ~90%. Compute cores on 7nm, I/O on 28nm, achieving global PPA optimization. Mitigating geopolitical risk and enhancing supply chain resilience.

🧠 PINN Physics-Informed AI Engine

White-box Innovation: Embedding physical laws (atmospheric dynamics) into neural networks, eliminating AI hallucinations at the source. Compared to pure data-driven "black box" models, achievingautomotive-grade absolute reliability in extreme scenarios. Proprietary IP forming an unreplicable technology moat.

📐 Model Quantization Technology

Compressing FP32 parameters to INT8/INT4,memory footprint reduced by ~75%, leveraging on-chip INT8 tensor cores for efficiency far exceeding floating-point operations.<50ms real-time response, like compressing 4K originals to JPEG — visual quality nearly lossless, efficiency improved 4x.

🔐 HSM Hardware Security Module

Co-developed with top research institutions, ASIL-C/D functional safety certified. Hardware-level data encryption, safeguarding edge device data sovereignty.

⚡ Ultra-Low Power Design

Patent-grade power managementArchitecture，dynamic voltage frequency scaling（DVFS）+ adaptive clock gating，edge scenariosPower Consumptionreduced to<15W，battery life improved3x。

🌡️ Wide-Temperature Reliability Design

-40°C to +125°C full-temperature stable operation, radiation-hardened design, meeting aerospace and automotive extreme environment reliability requirements.

🔧 Advanced Process Capability

Full process coverage from 7nm to 40nm, core team has advanced process R&D experience at TSMC, Samsung, and Qualcomm — the world's top three foundries.

🌐 Global Supply Chain Integration

Deep integration of world-class supply chain resources (TSMC, Samsung, Qualcomm), helping Chinese clients navigate overseas supply chain challenges, ensuring capacity and compliance.

Global Impact

Global Impact: From Technology Follower to Standard Leader

Actively participating in international standard-setting, driving global adoption of edge AI chip solutions

🌍 WMO MAZU Global Weather AI Agent

CHIPSTARS actively participates in global weather intelligence cooperation, providing chip design and technical consulting services to international meteorological organizations. Edge AI early warning technology has been validated and applied in international cooperation projects.

This marks CHIPSTARS' achievement of transitioning fromfollowing international standards to leading and exporting standards— a critical leap.

🎯 Our Role

Localization Speedboat — Rapidly capturing beachheads in AI inference acceleration, advanced packaging, and other niche segments — more agile than giants

Technology Translator — Not just selling chips, but connecting AI technology with traditional industry needs, providing complete solutions from top-level design to implementation

Venture Studio — Deeply integrating external top-tier technology with traditional industry scenarios, batch-incubating new species with international competitiveness

Roadmap

R&D Pipeline & Commercialization Path

From IP Licensing to Chip Mass Production, From Edge AI to Ubiquitous Intelligence

2021-2023 · Foundation Phase

Team Building & Technology Validation

Company founded, core team in place. TWS Bluetooth audio SoC chip mass-produced and shipped, validating chip design capability. Bluetooth IP licensing services verified. Foundational IP library completed.

2024-2025 · Breakthrough Phase

Edge AI Chip Productization

Low-power edge AI MCU released. RF IP licensing business expanded. Embodied intelligence chip prototype verified. Automotive electronics design service platform established.

2026 · Year of Embodied Intelligence Chip

Dexterous Hand Control Chip

Building a dedicated "Cerebellum" control chip for embodied intelligence, achieving millisecond tactile closed-loop response. Supporting 128-256 channel real-time sensor encoding and pattern matching, full-chain latency under 1ms, giving robots human-hand-like physical reflex capability.

2027-2028 · Expansion Phase

Multi-Scenario Scaling

Automotive electronics chip platform, aerospace chip mass production. Storage chip product line completion. Global customer expansion.

2029-2030 · Ecosystem Phase

Global Edge Compute Network

Millions of edge device compute nodes. Data services at scale. Edge AI chip full-scenario coverage.

Leadership

Founding Team

TSMC Liang Mong-song Line × Global Business Operator × Qualcomm Engineering DNA

Chen

Dr. Chen Jianliang

Founder / CEO

One of the six core members of TSMC's Liang Mong-song team, spanning TSMC, Samsung, and Qualcomm — the world's top three semiconductor companies. 20+ years of advanced process R&D experience, full process coverage from 130nm to 7nm. Apple order operator, Qualcomm Dresden General Manager. Mastering world-class foundry resources and supply chain networks.

20+

Years Industry Experience

TSMC

Liang Mong-song Line

Jacob

Co-Founder / Co-CEO

Leading a 50,000-member premium B2B enterprise alliance. A global business operator spanning technology, brand, and retail. Responsible for CHIPSTARS' global commercial strategy, customer ecosystem, and capital operations.

Fortune 500

Executive Background

50K+

CXO Community

Global Team Scale

65+

Global Employees

20+

Core Technical Leaders

Global R&D Centers

Core team from TSMC, Samsung, Qualcomm, UMC and other world-class semiconductor companies

NVIDIA Rules the CloudCHIPSTARSFocuses on Edge Compute

About

Making Every Edge Device a Distributed Compute Node

🎯 Strategic Positioning: Localization Backbone + Global Wings

🎯 Why Edge AI Is a Necessity

Centralized Compute vs Distributed Edge Compute

Product & Service Matrix

🤖 Embodied Intelligence Chip

📡 RF & Wireless Connectivity IP

🛰️ LEO Satellite Communication Chip

🚗 NEV Chip Design Service Platform

🧠 Edge AI Processor + Weather Neural Node

Embodied Intelligence: Millisecond Tactile Closed Loop

Distributed Edge Control, Leaving Centralized Compute Bottlenecks Behind

🔄 Millisecond Tactile Closed Loop Flow

🎯 Perception Training Ball

🧠 Sim-to-Real

🔄 Reinforcement Learning Closed Loop

Core Technology Moats

🔬 Chiplet Heterogeneous Integration

🧠 PINN Physics-Informed AI Engine

📐 Model Quantization Technology

🔐 HSM Hardware Security Module

⚡ Ultra-Low Power Design

🌡️ Wide-Temperature Reliability Design

🔧 Advanced Process Capability

🌐 Global Supply Chain Integration

Industry Ecosystem Partners

TSMC / Samsung / UMC

SMIC

Qualcomm

CAS (Chinese Academy of Sciences)

Tongji University

OEMs & Tier 1

RT-Thread

Global Impact: From Technology Follower to Standard Leader

🌍 WMO MAZU Global Weather AI Agent

🎯 Our Role

R&D Pipeline & Commercialization Path

Team Building & Technology Validation

Edge AI Chip Productization

Dexterous Hand Control Chip

Multi-Scenario Scaling

Global Edge Compute Network

Founding Team

Dr. Chen Jianliang

Jacob

Global Team Scale

Global

🇨🇳 China · Shanghai

🇩🇪 Germany · Dresden

🇬🇧 United Kingdom

Core Industry Partners

TSMC

Samsung

SMIC

UMC

Qualcomm

CAS (Chinese Academy of Sciences)

Tongji University

OEMs / Tier 1

Seeking Partnership & Growth

📧 Business Cooperation

📍 Company Headquarters

🌐 Global Presence

NVIDIA Rules the Cloud
CHIPSTARSFocuses on Edge Compute